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Features
* High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture
- 131 Powerful Instructions - Most Single-clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 20 MIPS Throughput at 20 MHz - On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments - 32K Bytes of In-System Self-programmable Flash program memory - 1K Bytes EEPROM - 2K Bytes Internal SRAM - Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM - Data retention: 20 years at 85C/ 100 years at 25C(1) - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Six PWM Channels - 8-channel, 10-bit ADC Differential mode with selectable gain at 1x, 10x or 200x - Byte-oriented Two-wire Serial Interface - Two Programmable Serial USART - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator - Interrupt and Wake-up on Pin Change Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages - 32 Programmable I/O Lines - 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF
*
*
*
8-bit Microcontroller with 32K Bytes In-System Programmable Flash
ATMEGA324PA
Summary
*
*
- 44-pad DRQFN - 49-ball VFBGA
* Operating Voltages
- 1.8 - 5.5V
* Speed Grades
- 0 - 20MHz @ 1.8 - 5.5V
* Power Consumption at 1 MHz, 1.8V, 25C
- Active: 0.4 mA - Power-down Mode: 0.1A - Power-save Mode: 0.6A (Including 32 kHz RTC)
8152AS-AVR-11/08
1. Pin Configurations
1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF
Figure 1-1. Pinout
PDIP
(PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 (PCINT29/OC1A) PD5 (PCINT30/OC2B/ICP) PD6 PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31)
TQFP/VQFN/QFN/MLF
PB4 (SS/OC0B/PCINT12) PB3 (AIN1/OC0A/PCINT11) PB2 (AIN0/INT2/PCINT10) PB1 (T1/CLKO/PCINT9) PB0 (XCK0/T0/PCINT8) GND VCC PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3)
(PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2
PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20)
Note:
The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.
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ATMEGA324PA
8152AS-AVR-11/08
(PCINT27/TXD1/INT1) (PCINT28/XCK1/OC1B) (PCINT29/OC1A) (PCINT30/OC2B/ICP) (PCINT31/OC2A)
PD3 PD4 PD5 PD6 PD7 VCC GND (PCINT16/SCL) PC0 (PCINT17/SDA) PC1 (PCINT18/TCK) PC2 (PCINT19/TMS) PC3
ATMEGA324PA
1.2 Pinout - DRQFN
Figure 1-2. DRQFN - Pinout
Top view
A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24
Bottom view
A24 B20 A23 B19 A22 B18 A21 B17 A20 B16 A19
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6
A18 B15 A17 B14 A16 B13 A15 B12 A14 B11 A13
A18 B15 A17 B14 A16 B13 A15 B12 A14 B11 A13 B4 B1
A1 A2 B2 A3 B3 A4 A5 B5 A6
A12 B10 A11 B9 A10 B8 A9 B7 A8 B6 A7
Table 1-1.
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6
DRQFN - Pinout
PB5 PB6 PB7 RESET VCC GND XTAL2 XTAL1 PD0 PD1 PD2 A7 B6 A8 B7 A9 B8 A10 B9 A11 B10 A12 PD3 PD4 PD5 PD6 PD7 VCC GND PC0 PC1 PC2 PC3 A13 B11 A14 B12 A15 B13 A16 B14 A17 B15 A18 PC4 PC5 PC6 PC7 AVCC GND AREF PA7 PA6 PA5 PA4 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 PA3 PA2 PA1 PA0 VCC GND PB0 PB1 PB2 PB3 PB4
B8 A10 B9 A11 B10 A12
B6 A7 A8
B7 A9
3
8152AS-AVR-11/08
1.3
Pinout - VFBGA
Figure 1-3. VFBGA - Pinout
Top view
1 A B C D E F G 2 3 4 5 6 7 7 6
Bottom view
5 4 3 2 1 A B C D E F G
Table 1-2.
BGA - Pinout
1 2 PB4 PB5 RESET XTAL2 PD1 PD3 PD4 3 PB2 PB3 PB7 PD0 PD5 PD6 VCC 4 GND PB0 PB1 GND PD7 PC0 GND 5 VCC PA0 PA1 PA4 PC5 PC2 PC1 6 PA2 PA3 PA6 PA7 PC7 PC4 PC3 7 GND PA5 AREF GND AVCC PC6 GND
A B C D E F G
GND PB6 VCC GND XTAL1 PD2 GND
4
ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
2. Overview
The ATMEGA324PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATMEGA324PA achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Block Diagram
Figure 2-1.
PA7..0
VCC
PB7..0
RESET
Power Supervision POR / BOD & RESET
PORT A (8)
PORT B (8)
GND
Watchdog Timer
Watchdog Oscillator
A/D Converter
Analog Comparator
USART 0
XTAL1
Oscillator Circuits / Clock Generation
EEPROM
Internal Bandgap reference
SPI
XTAL2
8bit T/C 0
CPU
JTAG/OCD
16bit T/C 1
TWI
FLASH
SRAM
8bit T/C 2
USART 1
PORT C (8)
PORT D (8)
TOSC2/PC7
TOSC1/PC6
PC5..0
PD7..0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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8152AS-AVR-11/08
The ATMEGA324PA provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel's high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATMEGA324PA is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATMEGA324PA AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
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ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
2.2
2.2.1
Pin Descriptions
VCC Digital supply voltage.
2.2.2
GND Ground.
2.2.3
Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATMEGA324PA as listed on page 81.
2.2.4
Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATMEGA324PA as listed on page 83.
2.2.5
Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of the JTAG interface, along with special features of the ATMEGA324PA as listed on page 86.
2.2.6
Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATMEGA324PA as listed on page 88.
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8152AS-AVR-11/08
2.2.7
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in "System and Reset Characteristics" on page 329. Shorter pulses are not guaranteed to generate a reset.
2.2.8
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.9
XTAL2 Output from the inverting Oscillator amplifier.
2.2.10
AVCC AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.2.11
AREF This is the analog reference pin for the Analog-to-digital Converter.
3. Resources
A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C.
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ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
5. Register Summary
Address
(0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1)
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR1 UBRR1H UBRR1L Reserved UCSR1C UCSR1B UCSR1A Reserved UDR0 UBRR0H UBRR0L Reserved UCSR0C UCSR0B
Bit 7
UMSEL11 RXCIE1 RXC1 UMSEL01 RXCIE0
Bit 6
UMSEL10 TXCIE1 TXC1 UMSEL00 TXCIE0
Bit 5
UDRIE1 UDRE1 UDRIE0
Bit 4
RXEN1 FE1 RXEN0
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Page
-
-
USART1 I/O Data Register USART1 Baud Rate Register High Byte TXEN1 DOR1 UDORD1 UCSZ12 UPE1 UCPHA1 RXB81 U2X1 UCPOL1 TXB81 MPCM1 USART1 Baud Rate Register Low Byte
190 194/207 194/207 192/206 191/205 190/205 190 USART0 Baud Rate Register High Byte 194/207 194/207 UDORD0 UCSZ02 UCPHA0 RXB80 UCPOL0 TXB80 192/206 191/205
USART0 I/O Data Register USART0 Baud Rate Register Low Byte TXEN0
9
8152AS-AVR-11/08
Address
(0xC0) (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F)
Name
UCSR0A Reserved Reserved TWAMR TWCR TWDR TWAR TWSR TWBR Reserved ASSR Reserved OCR2B OCR2A TCNT2 TCCR2B TCCR2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1
Bit 7
RXC0 TWAM6 TWINT TWA6 TWS7 -
Bit 6
TXC0 TWAM5 TWEA TWA5 TWS6 EXCLK -
Bit 5
UDRE0 TWAM4 TWSTA TWA4 TWS5 AS2 -
Bit 4
FE0 TWAM3 TWSTO TWA3 TWS4 TCN2UB -
Bit 3
DOR0 TWAM2 TWWC TWA2 TWS3 OCR2AUB -
Bit 2
UPE0 TWAM1 TWEN TWA1 OCR2BUB -
Bit 1
U2X0 TWAM0 TWA0 TWPS1 TCR2AUB -
Bit 0
MPCM0 TWIE TWGCE TWPS0 TCR2BUB -
Page
190/205
236 233 235 236 235 233 158 158 158 157
2-wire Serial Interface Data Register
2-wire Serial Interface Bit Rate Register
Timer/Counter2 Output Compare Register B Timer/Counter2 Output Compare Register A Timer/Counter2 (8 Bit) FOC2A COM2A1 FOC2B COM2A0 COM2B1 COM2B0 WGM22 CS22 CS21 WGM21 CS20 WGM20 -
156 153
Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte FOC1A ICNC1 COM1A1 FOC1B ICES1 COM1A0 COM1B1 WGM13 COM1B0 WGM12 CS12 CS11 WGM11 AIN1D CS10 WGM10 AIN0D
137 137 137 137 138 138 137 137 136 135 133 240
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ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
Address
(0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D)
Name
DIDR0 Reserved ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved PCMSK3 Reserved Reserved TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 Reserved EICRA PCICR Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved RAMPZ Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK
Bit 7
ADC7D REFS1 ADEN
Bit 6
ADC6D REFS0 ACME ADSC
Bit 5
ADC5D ADLAR ADATE
Bit 4
ADC4D MUX4 ADIF
Bit 3
ADC3D MUX3 ADIE
Bit 2
ADC2D MUX2 ADTS2 ADPS2
Bit 1
ADC1D MUX1 ADTS1 ADPS1
Bit 0
ADC0D MUX0 ADTS0 ADPS0
Page
260 256 239 258 259 259
ADC Data Register High byte ADC Data Register Low byte PCINT31 PCINT23 PCINT15 PCINT7 PRTWI CLKPCE WDIF I SP15 SP7 SPMIE JTD ACD SPIF0 SPIE0 PCINT30 PCINT22 PCINT14 PCINT6 PRTIM2 WDIE T SP14 SP6 RWWSB BODS ACBG WCOL0 SPE0 PCINT29 ICIE1 PCINT21 PCINT13 PCINT5 ISC21 PRTIM0 WDP3 H SP13 SP5 SIGRD BODSE ACO DORD0 PCINT28 PCINT20 PCINT12 PCINT4 ISC20 PRUSART1 WDCE S SP12 SP4 RWWSRE PUD JTRF ACI MSTR0 PCINT27 PCINT19 PCINT11 PCINT3 ISC11 PCIE3 PRTIM1 CLKPS3 WDE V SP11 SP3 BLBSET WDRF SM2 ACIE CPOL0 PCINT26 OCIE2B OCIE1B OCIE0B PCINT18 PCINT10 PCINT2 ISC10 PCIE2 PRSPI CLKPS2 WDP2 N SP10 SP2 PGWRT BORF SM1 ACIC CPHA0 PCINT25 OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 ISC01 PCIE1 PRUSART0 CLKPS1 WDP1 Z SP9 SP1 PGERS IVSEL EXTRF SM0 ACIS1 SPR01 PCINT24 TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 ISC00 PCIE0 -
71
159 138 110 71 71 72 68 70 41
Oscillator Calibration Register PRADC CLKPS0 WDP0 C SP8 SP0 RAMPZ0 SPMEN IVCE PORF SE -
49
41 60 11 12 12 15
290 92/276 59/276 48 266
On-Chip Debug Register ACIS0 -
258 171
SPI 0 Data Register SPI2X0 SPR00
170 169 29 29
General Purpose I/O Register 2 General Purpose I/O Register 1 Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0A COM0A1 TSM FOC0B COM0A0 COM0B1 COM0B0 EEPROM Data Register EEPM1 EEPM0 EERIE EEMPE INT2 EEPE INT1 EERE INT0 General Purpose I/O Register 0 WGM02 CS02 CS01 WGM01 PSRASY CS00 WGM00 PSR5SYNC
110 109 109 108 110 160 24 24 24 24 29 69
EEPROM Address Register High Byte
EEPROM Address Register Low Byte
11
8152AS-AVR-11/08
Address
0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
EIFR PCIFR Reserved Reserved Reserved TIFR2 TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA
Bit 7
PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7
Bit 6
PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6
Bit 5
ICF1 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5
Bit 4
PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4
Bit 3
PCIF3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3
Bit 2
INTF2 PCIF2 OCF2B OCF1B OCF0B PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2
Bit 1
INTF1 PCIF1 OCF2A OCF1A OCF0A PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1
Bit 0
INTF0 PCIF0 TOV2 TOV1 TOV0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0
Page
69 70
160 139 110
93 93 93 93 93 93 92 92 92 92 92 92
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATMEGA324PA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
12
ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
6. Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 4 4 5 5 5 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr
1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1
PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1
R1:R0 (Rd x Rr) <<
BRANCH INSTRUCTIONS
13
8152AS-AVR-11/08
Mnemonics
BRVC BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH k k k
Operands
Description
Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
Operation
if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 R0 (RAMPZ:Z) Rd (Z) Rd (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1
Flags
None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1/2 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3
BIT AND BIT-TEST INSTRUCTIONS P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM ELPM ELPM ELPM Rd, Z Rd, Z+ Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Extended Load Program Memory Extended Load Program Memory Extended Load Program Memory
14
ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
Mnemonics
SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd
Operands
Store Program Memory In Port Out Port Push Register on Stack
Description
(Z) R1:R0 Rd P P Rr STACK Rr Rd STACK
Operation
Flags
None None None None None None
#Clocks
1 1 2 2 1 1 1 N/A
Pop Register from Stack No Operation Sleep Watchdog Reset Break
MCU CONTROL INSTRUCTIONS (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None
15
8152AS-AVR-11/08
7. Ordering Information
7.1 ATMEGA324PA
Power Supply Ordering Code(2) ATMEGA324PA-AU ATMEGA324PA-PU ATMEGA324PA-MU ATMEGA324PA-MCH(4) ATMEGA324PA-CU Package(1) 44A 40P6 44M1 44MC 49C2 Operational Range
Speed (MHz)(3)
20
1.8 - 5.5V
Industrial (-40oC to 85oC)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed Grades" on page 327. 4. NiPdAu Lead Finish.
Package Type 44A 40P6 44M1 44MC 49C2 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN) 49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
16
ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
8. Packaging Information
8.1 44A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
17
8152AS-AVR-11/08
8.2
40P6
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 L C eB e
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B
R
18
ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
8.3 44M1
D
Marked Pin# 1 ID
E
SEATING PLANE
TOP VIEW
A1 A3
K L D2
Pin #1 Corner
A
SIDE VIEW
1 2 3
Option A
Pin #1 Triangle
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.80 - NOM 0.90 0.02 0.20 REF 0.18 6.90 5.00 6.90 5.00 0.23 7.00 5.20 7.00 5.20 0.50 BSC 0.59 0.20 0.64 0.26 0.69 0.41 0.30 7.10 5.40 7.10 5.40 MAX 1.00 0.05 NOTE
E2
Option B
Pin #1 Chamfer (C 0.30)
A A1 A3 b D
K b e
Option C
Pin #1 Notch (0.20 R)
D2 E E2 e L
BOTTOM VIEW
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
K
9/26/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) GPC ZWS DRAWING NO. 44M1 REV. H
19
8152AS-AVR-11/08
8.4
44MC
C
Pin 1 ID
D
SIDE VIEW
y
E A
A1
TOP VIEW
eT/2
A19 A24 B16 B20 A1 B15 B1
eR
A18
b R0.20 D2 eT
B11 A13 B10 A12 B6 A7 B5 A6
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 b C D D2 E 4.90 2.55 4.90 2.55 - - 0.45 0.30 0.00 MIN 0.80 0.00 0.18 NOM 0.90 0.02 0.23 0.20 REF 5.00 2.60 5.00 2.60 0.70 0.40 - 0.35 - 5.10 2.65 5.10 2.65 - - - 0.40 0.075 MAX 1.00 0.05 0.30 NOTE
0.40
L
E2
L
L
E2 eT
BOTTOM VIEW
eR K L
Note:
1. The terminal #1 ID is a Laser-marked Feature.
y
Package Drawing Contact: packagedrawings@atmel.com
TITLE 44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00 mm Body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No Lead Package
9/13/07 DRAWING NO. REV. 44MC A
20
ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
8.5 49C2
E
A1 BALL ID
0.10
D
A1
TOP VIEW
A A2
SIDE VIEW
E1
G
e
F E D C B A
1 2 3 4 5 6 7
D1
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 MIN - 0.20 0.65 4.90 NOM - - - 5.00 3.90 BSC 4.90 5.00 3.90 BSC 0.30 0.35 0.65 BSC 0.40 5.10 MAX 1.00 - - 5.10 NOTE
A1 BALL CORNER
b
BOTTOM VIEW
e
49 - O0.35 0.05
A2 D D1 E E1 b e
3/14/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 49C2, 49-ball (7 x 7 Array), 0.65 mm Pitch, 5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GPC CBD DRAWING NO. 49C2 REV. A
21
8152AS-AVR-11/08
9. Errata
9.1 ATMEGA324PA Rev. F
No known Errata.
22
ATMEGA324PA
8152AS-AVR-11/08
ATMEGA324PA
10. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.
10.1
Rev. 8152A- 11/08
1. 2.
Initial revision (Based on the ATmega164P/324P/644P datasheet 8011K-AVR-09/08). Changes done compared to ATmega164P/324P/644P datasheet 8011K-AVR-09/08: - New graphics in "Typical Characteristics" on page 336
- New "Ordering Information" on page 16
23
8152AS-AVR-11/08
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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8152AS-AVR-11/08

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